The present invention relates generally to a novel method and apparatus for inspecting a semiconductor wafer for defects.
Integrated circuits (ICs) are commonly manufactured through a series of processing steps. Very often more than a hundred processing steps are performed to produce a properly functioning integrated circuit chip.
A semiconductor material, commonly in the shape of a wafer, serves as the substrate for integrated circuits. Semiconductor ICs are typically manufactured as an assembly of a hundred or more chips on a single semiconductor wafer which is then cut up to produce the individual IC chips. Typically, a wafer made of silicon is used as the integrated circuit substrate, the silicon wafer being approximately 150–300 mm in diameter and 0.6–1 mm thick. During the manufacturing process, the silicon wafer is first polished and cleaned to remove all contaminant particles situated thereon. The silicon wafer is then treated in preparation for a series of processing steps involving a plurality of photolithographic patterns (also commonly referred to as masks). In the production of integrated circuits, microelectronic circuits are formed onto the silicon wafer through a process of layering. In the layering process, conductive and insulated layers of thin films are deposited and patterned onto the silicon wafer. Each layer is patterned by a mask designed specifically for it, the mask defining the areas within the wafer that are to be treated such as by etching or implanting.
Semiconductor fabrication technology today deals with silicon wafers which are approximately 200 mm in diameter and which feature geometries with dimensions well below 0.5 μm (micrometer). Due to the high complexity and level of integration of integrated circuits, the absence of defects on every layer of the wafer is critical in order to realize acceptable levels of product yield. The most prevalent type of wafer pattern defect which occurs during the manufacturing of patterned semiconductor wafers is the improper deposition of conductive and/or insulated material onto the silicon wafer during the layering process. Additional types of wafer pattern defects include, inter alia, the presence of contaminant particles and/or scratches on the wafer during the manufacturing process.
As can be appreciated, the presence of a single defect larger than half the width of a conductive line on the silicon wafer can result in the complete failure of a semiconductor chip which is produced from the wafer. Such a chip has to be discarded which thereby decreases the percentage yield per wafer and increases the overall cost of the individual wafers. Therefore, a critical task facing semiconductor process engineers is to identify and, as soon as possible, to eliminate sources of defects on each layer of a semiconductor wafer.
Accordingly, wafer inspection systems are well known in the art and are commonly used to detect, identify and correct yield limiting defects which are introduced onto the surface of a semiconductor wafer during the fabrication process of integrated circuits. In fact, it is well known in the art for a plurality of wafer inspection systems to be used to inspect a semiconductor wafer at various points in time during the fabrication of said semiconductor wafer. As such, each wafer inspection system serves to inspect the semiconductor wafer after the treatment of a particular layer of the integrated circuit. By using multiple wafer inspection instruments to scan various layers of the semiconductor wafer for defects, the user is able to discern where, and more specifically on which layer, a defect first occurred during the manufacturing process. The ability to discern where a defect first occurred is extremely useful in removing the defect and in preventing future defects.
Wafer Inspection systems typically include at least one light source (e.g., a laser) which illuminates an area on the surface of the wafer. A main imaging camera is positioned directly above the surface of the wafer and detects light which is scattered from the area illuminated by the light source. A main imaging lens is disposed between the surface of the wafer and the main imaging camera and serves to image the illuminated area on the semiconductor wafer onto the main imaging camera. The main imaging camera is typically connected to an image processing computer which identifies and stores the location of each defect. A wafer defect map is then generated and displayed on a monitor or is used to track the defects through further processing layers. In this manner, a semiconductor process engineer is capable of locating the presence of defects on a semiconductor wafer by viewing the viewing screen of the monitor, which is highly desirable.
Wafer inspection systems of the type described above have been made commercially available by such companies as Inspex, Inc. of Billerica, Mass. The EAGLE™ wafer inspection system is one well known type of wafer inspection system which is manufactured and sold by Inspex, Inc. of Billerica, Mass. Examples of some well-known wafer inspection systems are shown in U.S. Pat. No. 6,621,570 and U.S. Pat. No. 5,805,278, which are both incorporated herein by reference.
Although well known and widely used in commerce to detect the presence of defects, conventional wafer inspection systems may suffer from a notable drawback. Specifically, the relatively high levels of magnification and optimization of the main imaging lens of a conventional wafer inspection system serves to significantly decrease the depth of field for the system (i.e., the allowable change in distance between the main imaging lens and the wafer surface while maintaining the wafer surface in focus). In fact, wafer inspection systems of the type described above have been found to have a depth of field in the order of approximately 2 microns.
However, it should be noted that wafer inspection systems commonly include a vacuum chuck for retaining the wafer to be inspected. In use, it has been found that a vacuum chuck can significantly deform an otherwise flat wafer mounted thereon. In fact, it has been found that vertical deviations in wafer topology can reach levels as high as 10 to 20 microns. Because vertical deviations in wafer topology are considerably greater than the depth of field of conventional wafer inspection systems, particular regions on a wafer scanned by a conventional wafer inspection system are often examined out of focus, which is highly undesirable.
Accordingly, it is the principal object of the present invention to provide a wafer inspection system with a dynamic, real-time auto-focusing system which can be used to vertically manipulate the wafer stage as deemed necessary to maintain each illuminated area on the wafer in focus regardless of whether the wafer is experiencing levels of considerable deformation.